PROG 001: 31 25 11 002: 31 22 01 003: 35 22 004: 31 25 01 005: 31 22 02 006: 35 22 007: 31 25 02 008: 31 22 03 009: 35 22 010: 31 25 03 011: 35 22 012: 84 HP67 Logging started. Note: when working through the microcode, major significant points are: 00167 - 00213; wait loop (for keypress, or card) 00256 a -> rom address; key press despatch - i.e. switch (keycode) { ... } - once per key press 06027 a -> rom address; prog step despatch - switch (prog_hex_code) { ... } - once per merged keycode Add a blank line after every occurance of each (00167 - 00213 wait loop) [A] 00214 display off ... 00256 a -> rom address 01466 ... 06027 a -> rom address ; GSB A ; ===== 06013 ... *** ram[61] -> c (=00000000000000) 06110 if c[x] # 0 06111 then go to 06114 06112 delayed rom 00 06113 jsb 0022 *** ram[61] -> c (=00000000000000) *** c -> ram[61] (=0000000000062f) ; was 000 so set step 001 06114 ... *** ram[47] -> c (=f20eb2f10eb1fa) ; get prgm steps 06243 jsb 0004 *** ram[61] -> c (=0000000000062f) ; get current step 06244 ... *** c -> ram[61] (=0000000000062f) ; found LBL A in step 001 00063 ... 00135 b -> c[w] 00136 if 1 = s 2 ; if running 00137 then go to 0304 00304 0 -> s 15 00305 if 0 = s 15 ; if not key_press 00306 then go to 0353 00353 CRC 500 00354 jsb 0004 ; get current step: ram[61] -> c (=0000000000062f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (fa) 00356 display toggle 00357 ... 06027 a -> rom address ; 001 LBL A ; ========= 06017 ... *** ram[61] -> c (=0000000000062f) ; get current step, 001 *** c -> ram[61] (=0000000000052f) ; step++ 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000000000052f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (b1) 00356 display toggle 00357 ... 06027 a -> rom address ; 002 GSB 1 ; ========= 06013 ... 06106 delayed rom 00 06107 jsb 0004 ; get current step: ram[61] -> c (=0000000000052f), 002 06110 ... *** ram[47] -> c (=f20eb2f10eb1fa) ; get prgm steps 06242 delayed rom 00 06243 jsb 0004 ; get current step: ram[61] -> c (=0000000000052f) =002 06244 if 0 = s 8 ; if GTO skip next bit 06245 then go to 06262 ... 06250 shift left a[wp] ; current step to return stack 06251 shift left a[wp] 06252 shift left a[wp] ... 06262 ... *** c -> ram[61] (=0000000052f32f) ; RTN=002, found LBL 1 in step 004 00063 ... 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000000052f32f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (f1) 00356 display toggle 00357 ... 06027 a -> rom address ; 004 LBL 1 ; ========= 06017 ... *** ram[61] -> c (=0000000052f32f) ; get current step 004 *** c -> ram[61] (=0000000052f22f) ; step++ 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000000052f22f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (b2) 00356 display toggle 00357 ... 06027 a -> rom address ; 005 GSB 2 ; ========= 06013 ... *** ram[61] -> c (=0000000052f22f) ; get current step 005 *** ram[47] -> c (=f20eb2f10eb1fa) ; get prgm steps *** ram[61] -> c (=0000000052f22f) *** c -> ram[61] (=0000052f22f02f) ; RTN=002,005 found LBL 2 in 007 00063 ... 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000052f22f02f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (=f2) 00356 display toggle 00357 ... 06027 a -> rom address ; 007 LBL 2 ; ========= 06017 ... *** ram[61] -> c (=0000052f22f02f) ; get current step 007 *** c -> ram[61] (=0000052f22f62e) ; step++ 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000052f22f62e) 00355 jsb 0011 ; get prgm steps : ram[46] -> c (=0000000ef30eb3) ; current prgm step now in a[1,0] (=b3) 00356 display toggle 00357 ... 06027 a -> rom address ; 008 GSB 3 ; ========= 06013 ... *** ram[61] -> c (=0000052f22f62e) ; get current step 008 *** ram[46] -> c (=0000000ef30eb3) ; get prgm steps *** ram[61] -> c (=0000052f22f62e) *** c -> ram[61] (=0052f22f62e42e) ; RTN=002,005,008 found LBL 3 in 010 00063 ... 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0052f22f62e42e) 00355 jsb 0011 ; get prgm steps : ram[46] -> c (=0000000ef30eb3) ; current prgm step now in a[1,0] (=f3) 00356 display toggle 00357 ... 06027 a -> rom address ; 010 LBL 3 ; ========= 06017 ... *** ram[61] -> c (=0052f22f62e42e) ; get current step 010 *** c -> ram[61] (=0052f22f62e32e) ; step++ 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0052f22f62e32e) 00355 jsb 0011 ; get prgm steps : ram[46] -> c (=0000000ef30eb3) ; current prgm step now in a[1,0] (=0e) 00356 display toggle 00357 ... 06027 a -> rom address ; 011 RTN ; ======= 06000 if n/c go to 06034 06034 decimal 06035 shift left a[x] 06036 delayed rom 015 06037 a -> rom address ; RTN 06416 ... *** ram[61] -> c (=0052f22f62e32e) ; get call stack 07274 if 1 = s 1 ; if SST 07275 then go to 07300 07276 if 0 = s 2 ; if not running 07277 then go to 06363 07300 0 -> c[s] ; get RTN addr 07301 shift right c[w] 07302 shift right c[w] 07303 shift right c[w] 07304 if c[w] # 0 07305 then go to 07310 07310 c -> data *** c -> ram[61] (=0000052f22f62e) ; save popped call stack 07311 if 1 = s 1 07312 then go to 07306 07313 delayed rom 00 07314 if n/c go to 0074 00074 ... 00134 jsb 0116 *** ram[61] -> c (=0000052f22f62e) ; get current step (008 f GSB 3) *** c -> ram[61] (=0000052f22f52e) ; step++ (009 ie after the GSB) 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000052f22f52e) 00355 jsb 0011 ; get prgm steps : ram[46] -> c (=0000000ef30eb3) ; current prgm step now in a[1,0] (=0e) 00356 display toggle 00357 ... 06027 a -> rom address ; 009 RTN ; ======= 06000 ... 06037 a -> rom address 06416 ... *** ram[61] -> c (=0000052f22f52e) ; get call stack *** c -> ram[61] (=0000000052f22f) ; save popped call stack 00074 ... 00134 jsb 0116 *** ram[61] -> c (=0000000052f22f) ; get current step (005 f GSB 2) *** c -> ram[61] (=0000000052f12f) ; step++ (006, after GSB) 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000000052f12f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (=0e) 00356 display toggle 00357 ... 06027 a -> rom address ; 006 RTN ; ======= 06000 ... 06037 a -> rom address 06416 ... *** ram[61] -> c (=0000000052f12f) ; get call stack *** c -> ram[61] (=0000000000052f) ; save popped stack 00074 ... 00134 jsb 0116 *** ram[61] -> c (=0000000000052f) ; get current step (002 f GSB 1) *** c -> ram[61] (=0000000000042f) ; step++ (003, after GSB) 00135 ... 00354 jsb 0004 ; get current step: ram[61] -> c (=0000000000042f) 00355 jsb 0011 ; get prgm steps : ram[47] -> c (=f20eb2f10eb1fa) ; current prgm step now in a[1,0] (=0e) 00356 display toggle 00357 ... 06027 a -> rom address ; 003 RTN ; ======= 06000 ... 06037 a -> rom address 06416 ... *** ram[61] -> c (=0000000000042f) ; get call stack 07300 0 -> c[s] ; get RTN address 07301 shift right c[w] 07302 shift right c[w] 07303 shift right c[w] 07304 if c[w] # 0 ; RTN=000 07305 then go to 07310 07306 delayed rom 00 07307 if n/c go to 0061 ; 00061 0 -> s 2 ; set running false 00062 jsb 0022 *** ram[61] -> c (=0000000000042f) ; current step (003 RTN) *** c -> ram[61] (=0000000000032f) ; step++ 00063 ... 00135 b -> c[w] 00136 if 1 = s 2 00137 then go to 0304 ; not this time 00140 0 -> c[w] 00141 0 -> s 1 ; set SST false 00142 0 -> s 3 00143 0 -> c[s] 00144 m1 exch c 00145 if 1 = s 11 00146 then go to 0317 00147 delayed rom 017 00150 jsb 07706 *** ram[63] -> c (=00000000000000) ; ??? 00151 a exchange b[w] 00152 a -> b[w] 00153 if 1 = s 12 00154 then go to 0157 00155 delayed rom 04 00156 jsb 02007 *** ram[62] -> c (=00000012220000) ; display format 00157 delayed rom 02 00160 jsb 01162 00161 hi im woodstock 00162 display off 00163 display toggle 00164 0 -> s 15 00165 if 1 = s 15 00166 then go to 0164 00167 - 00213 wait loop aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa This is another trace through with more detail and a slightly different program aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa HP67 Logging started. (00167 - 00213 wait loop) [A] (00214 - 00256 keypress routine)(key=a4) key_a_start: (A=0000fffffff360 F=00000000000000 M1=03000000000400) (B=00000000000000 E=00000000000000 M2=00000000000000) (C=00000000000000 D=00000000000000 S=.........9.....f P=1) 01466 if n/c go to 01660 01660 if 1 = s 8 01661 then go to 01670 01662 if 1 = s 7 01663 then go to 01474 01664 if 1 = s 6 01665 then go to 01670 01666 if 1 = s 10 01667 then go to 01474 01670 0 -> s 3 01671 CRC 1100 ; test default functions flag. 01672 if 1 = s 3 01673 then go to 01676 ; 01674 load constant 11 ; C=000000000000b0 P=0 01675 if n/c go to 01474 01474 c + 1 -> c[x] ; C=000000000000b1 01475 c + 1 -> c[x] ; C=000000000000b2 01476 p <- 8 01477 c + 1 -> c[x] ; C=000000000000b3 01500 p - 1 -> p ; P=7 01501 if p # 0 01502 then go to 01477 ; C=000000000000b4 P=6 ; C=000000000000b5 P=5 ; C=000000000000b6 P=4 ; C=000000000000b7 P=3 ; C=000000000000b8 P=2 ; C=000000000000b9 P=1 ; C=000000000000ba P=0 ; note "ba" is hex code for "GSB A" 01501 if p # 0 01502 then go to 01477 01503 if n/c go to 01566 01566 delayed rom 01 01567 if n/c go to 0437 00437 c -> a[w] ; A=000000000000ba 00440 m1 exch c ; M1=000000000000ba C=03000000000400 00441 delayed rom 02 (00442 jsb 01205; 0 -> s 4 6 7 8 10 13) ; S=.........9.....f 00443 if 1 = s 11 00444 then go to 0340 00445 delayed rom 014 00446 if n/c go to 06021 06021 m1 -> c ; C=000000000000ba 06022 c -> a[x] ; A=000000000000ba 06023 0 -> a[xs] ; A=000000000000ba 06024 b -> c[w] ; C=00000000000000 06025 p <- 12 06026 0 -> s 3 ; S=.........9.....f 06027 a -> rom address ; a[2]=0 a[1]=b =1011 =013; pc & !0xff = 06000; pc= 6013 ; all of the 0xbN hex codes go here (GSB 0-9,A-E,i) 06013 if n/c go to 06052 06052 1 -> s 8 ; S=........89.....f 06053 p <- 1 06054 a + 1 -> a[p] ; A=000000000000ca 06055 a + 1 -> a[p] ; A=000000000000da 06056 p <- 1 06057 a + 1 -> a[p] ; A=000000000000ea 06060 a + 1 -> a[p] ; A=000000000000fa ; this is hex code for "f LBL A" 06061 p <- 0 06062 b -> c[w] ; C=00000000000000 06063 m1 exch c ; M1=00000000000000 C=000000000000ba 06064 a + 1 -> a[p] ; A=000000000000fb 06065 if n/c go to 06071 06071 a - 1 -> a[p] ; A=000000000000fa 06072 a exchange c[w] ; A=000000000000ba C=000000000000fa 06073 p <- 1 06074 c -> a[w] ; A=000000000000fa 06075 shift left a[w] ; A=00000000000fa0 06076 shift left a[w] ; A=0000000000fa00 06077 a exchange c[xs] ; A=0000000000f000 C=00000000000afa 06100 shift left a[w] ; A=000000000f0000 06101 shift left a[w] ; A=00000000f00000 06102 c -> a[x] ; A=00000000f00afa 06103 p - 1 -> p ; P=0 06104 if p # 5 06105 then go to 06100 ; A=000000f00afafa P=13 ; A=0000f00afafafa P=12 ; A=00f00afafafafa P=11 ; A=f00afafafafafa P=10 ; A=0afafafafafafa P=9 ; A=fafafafafafafa P=8 ; A=fafafafafafafa P=7 ; A=fafafafafafafa P=6 ; A=fafafafafafafa P=5 06104 if p # 5 06105 then go to 06100 06106 delayed rom 00 06107 jsb 0004 .00004 p <- 1 .00005 load constant 3 ; C=00000000000a3a .00006 c -> addr ; *** ram_addr=58 .00007 data register -> c 13 ; C=00000000000000 =ram[61] .00010 return 06110 if c[x] # 0 ; check 2,1,0 06111 then go to 06114 06112 delayed rom 00 06113 jsb 0022 ; (step++) .00022 delayed rom 05 .00023 if n/c go to 02660 .02660 p <- 1 .02661 load constant 3 ; C=00000000000030 .02662 c -> addr ; *** ram_addr=48 .02663 data register -> c 13 ; C=00000000000000 =ram[61] .02664 c - 1 -> c[xs] ; C=00000000000f00 .02665 if n/c go to 02704 .02666 p <- 2 .02667 load constant 6 ; C=00000000000600 P=1 .02670 p <- 0 .02671 c - 1 -> c[p] ; C=0000000000060f .02672 if n/c go to 02704 .02673 load constant 15 ; C=0000000000060f P=13 .02674 p <- 1 .02675 if c[p] = 0 .02676 then go to 02703 .02703 load constant 2 ; C=0000000000062f P=0 .02704 delayed rom 00 .02705 if n/c go to 0024 .00024 c -> data register 13 ; *** ram[61]=0000000000062f (step=001) .00025 return 06114 p <- 1 06115 p - 1 -> p ; P=0 06116 p - 1 -> p ; P=13 06117 c - 1 -> c[xs] ; C=0000000000052f 06120 if n/c go to 06115 ; C=0000000000042f P=11 ; C=0000000000032f P=9 ; C=0000000000022f P=7 ; C=0000000000012f P=5 ; C=0000000000002f P=3 ; C=00000000000f2f P=1 06120 if n/c go to 06115 06121 c -> addr ; *** ram_addr=47 (ram bank 2, register 0x0f) 06122 b exchange c[w] ; B=00000000000f2f C=00000000000000 06123 data -> c ; C=f20eb2f10eb1fa (steps 7,6,5,4,3,2,1) 06124 b exchange c[w] ; B=f20eb2f10eb1fa C=00000000000f2f 06125 a exchange b[w] ; A=f20eb2f10eb1fa B=fafafafafafafa 06126 if a >= b[p] 06127 then go to 06205 06205 a exchange b[p] ; A=f20eb2f10eb1fa B=fafafafafafafa 06206 if a >= b[p] ; note this is now checking == 06207 then go to 06212 06212 a exchange b[p] ; A=f20eb2f10eb1fa B=fafafafafafafa (put it back) 06213 p - 1 -> p ; P=0 06214 if a >= b[p] 06215 then go to 06220 06220 a exchange b[p] ; A=f20eb2f10eb1fa B=fafafafafafafa 06221 if a >= b[p] 06222 then go to 06225 ; if A[n+1,n] == B[n+1,n] 06225 c + 1 -> c[xs] ; C=0000000000002f 06226 p - 1 -> p ; P=13 06227 p - 1 -> p ; P=12 06230 if p # 12 06231 then go to 06225 06232 c + 1 -> c[xs] ; C=0000000000012f 06233 c + 1 -> c[xs] ; C=0000000000022f 06234 c + 1 -> c[xs] ; C=0000000000032f 06235 decimal 06236 0 - c - 1 -> c[xs] ; C=0000000000062f 06237 c -> a[w] ; A=0000000000062f 06240 m1 -> c ; C=00000000000000 06241 b exchange c[w] ; B=00000000000000 C=fafafafafafafa 06242 delayed rom 00 06243 jsb 0004 (as above) ; get ram[61] to C=0000000000062f 06244 if 0 = s 8 06245 then go to 06262 06246 a exchange c[w] ; A=0000000000062f C=0000000000062f 06247 p <- 11 ; this is saving the return address 06250 shift left a[wp] ; A=000000000062f0 06251 shift left a[wp] ; A=00000000062f00 06252 shift left a[wp] ; A=0000000062f000 ; 06253 a exchange c[w] ; A=0000000000062f C=0000000062f000 06254 if 1 = s 2 06255 then go to 06262 06256 1 -> s 2 ; S=..2.....89.....f 06257 if 1 = s 1 06260 then go to 06262 ; (from the keyboard: don't save return address)? 06261 0 -> c[w] ; C=00000000000000 06262 a exchange c[x] ; A=00000000000000 C=0000000000062f 06263 c -> data register 13 ; *** ram[61]=0000000000062f 06264 delayed rom 00 06265 if n/c go to 0063 ; ; set lift stack flag 00063 1 -> s 9 ; S=..2.....89.....f ; 00064 binary 00065 CRC 1500 ; ?C pause 00066 CRC 1300 ; ?C merge 00067 0 -> s 12 ; no input (S=..2.....89.....f) 00070 delayed rom 02 00071 jsb 01205 (0 -> s 4 6 7 8 10 13) ; S=..2......9.....f 00072 if n/c go to 0135 00135 b -> c[w] ; C=00000000000000 00136 if 1 = s 2 00137 then go to 0304 ; ; check if keypress during program (e.g. R/S) 00304 0 -> s 15 00305 if 0 = s 15 00306 then go to 0353 ; 00353 CRC 500 ; keypress? (S=..23.....9......) 00354 jsb 0004 ; get step (ram[61]) C=0000000000062f 00355 jsb 0011 .00011 c -> a[x] ; A=0000000000062f .00012 c -> addr ; *** ram_addr=47 .00013 data -> c ; C=f20eb2f10eb1fa .00014 a exchange c[w] ; A=f20eb2f10eb1fa C=0000000000062f .00015 rotate a left ; A=20eb2f10eb1faf .00016 rotate a left ; A=0eb2f10eb1faf2 .00017 c - 1 -> c[xs] ; C=0000000000052f .00020 if n/c go to 0015 ; A=b2f10eb1faf20e C=0000000000042f ; A=f10eb1faf20eb2 C=0000000000032f ; A=0eb1faf20eb2f1 C=0000000000022f ; A=b1faf20eb2f10e C=0000000000012f ; A=faf20eb2f10eb1 C=0000000000002f ; A=f20eb2f10eb1fa C=00000000000f2f .00020 if n/c go to 0015 .00021 return 00356 display toggle 00357 a exchange c[w] ; A=00000000000f2f C=f20eb2f10eb1fa 00360 m1 exch c ; M1=f20eb2f10eb1fa C=00000000000000 00361 delayed rom 014 00362 if n/c go to 06021 06021 m1 -> c ; C=f20eb2f10eb1fa 06022 c -> a[x] ; A=000000000001fa 06023 0 -> a[xs] ; A=000000000000fa ("fa" is the instruction: f LBL A) 06024 b -> c[w] ; C=00000000000000 06025 p <- 12 06026 0 -> s 3 06027 a -> rom address ; pc & !0xff -> 06000, a[2,1]="0f" = 0000 1111 = 00 001 111 = 017 ; ; all of the 0xfN hex codes go here (LBL 0-9,A-E,spare=i) ; 06017 delayed rom 00 06020 if n/c go to 0074 ; (00074 - ... A=000000000000fa F=00000000000000 M1=f20eb2f10eb1fa B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 00134 jsb 0116 .00116 if 1 = s 2 .00117 then go to 0122 .00122 if n/c go to 0022 ; ; we've been here before .00022 delayed rom 05 .00023 if n/c go to 02660 .02660 p <- 1 .02661 load constant 3 .02662 c -> addr ; *** ram_addr=48 .02663 data register -> c 13 ; C=0000000000062f .02664 c - 1 -> c[xs] ; C=0000000000052f .02665 if n/c go to 02704 .02704 delayed rom 00 .02705 if n/c go to 0024 .00024 c -> data register 13 ; *** ram[61]=0000000000052f .00025 return ; 00135 b -> c[w] ; C=00000000000000 00136 if 1 = s 2 ; ? running 00137 then go to 0304 00304 0 -> s 15 ; S=..2......9...... 00305 if 0 = s 15 00306 then go to 0353 00353 CRC 500 00354 jsb 0004 .00004 p <- 1 .00005 load constant 3 .00006 c -> addr ; *** ram_addr=48 .00007 data register -> c 13 ; C=0000000000052f .00010 return 00355 jsb 0011 .00011 c -> a[x] ; A=0000000000052f .00012 c -> addr ; *** ram_addr=47 .00013 data -> c ; C=f20eb2f10eb1fa .00014 a exchange c[w] ; A=f20eb2f10eb1fa C=0000000000052f .00015 rotate a left ; A=20eb2f10eb1faf .00016 rotate a left ; A=0eb2f10eb1faf2 .00017 c - 1 -> c[xs] ; C=0000000000042f .00020 if n/c go to 0015 ; A=b2f10eb1faf20e C=0000000000032f ; A=f10eb1faf20eb2 C=0000000000022f ; A=0eb1faf20eb2f1 C=0000000000012f ; A=b1faf20eb2f10e C=0000000000002f ; A=faf20eb2f10eb1 C=00000000000f2f .00020 if n/c go to 0015 .00021 return 00356 display toggle 00357 a exchange c[w] ; A=00000000000f2f C=faf20eb2f10eb1 00360 m1 exch c ; M1=faf20eb2f10eb1 C=f20eb2f10eb1fa 00361 delayed rom 014 00362 if n/c go to 06021 06021 m1 -> c ; C=faf20eb2f10eb1 06022 c -> a[x] ; A=00000000000eb1 06023 0 -> a[xs] ; A=000000000000b1 06024 b -> c[w] ; C=00000000000000 06025 p <- 12 06026 0 -> s 3 ; S=..2......9...... 06027 a -> rom address ; pc=06000, a[2,1]="0b" =0000 1011 =00 001 011 =013 ; all of the 0xbN hex codes go here (GSB 0-9,A-E,i) 06013 if n/c go to 06052 (we've seen this before) (b1 is "GSB 1". translated to f1 "f LBL 1") (-06103) until A=f1f1f1f1f1f1f1 P=5 06104 if p # 5 06105 then go to 06100 06106 delayed rom 00 06107 jsb 0004 (get step to C) C=0000000000052f 06110 if c[x] # 0 06111 then go to 06114 ; === set p to next instruction position in register 06114 p <- 1 06115 p - 1 -> p ; P=0 06116 p - 1 -> p ; P=13 06117 c - 1 -> c[xs] ; C=0000000000042f 06120 if n/c go to 06115 ; C=0000000000032f P=11 ; C=0000000000022f P=9 ; C=0000000000012f P=7 ; C=0000000000002f P=5 ; C=00000000000f2f P=3 06120 if n/c go to 06115 ; === ; === get register containing current/next instruction 06121 c -> addr ; *** ram_addr=47 06122 b exchange c[w] ; B=00000000000f2f C=00000000000000 06123 data -> c ; C=f20eb2f10eb1fa 06124 b exchange c[w] ; B=f20eb2f10eb1fa C=00000000000f2f 06125 a exchange b[w] ; A=f20eb2f10eb1fa B=f1f1f1f1f1f1f1 ; === ; === for (; instruction at p != target; p+=2) 06126 if a >= b[p] 06127 then go to 06205 06130 p + 1 -> p ; P=4 06131 p + 1 -> p ; P=5 ; if (p is too much) 06132 if p # 0 06133 then go to 06126 ; (n/a but get next set of 7 instructions) ; P=7 06126 if a >= b[p] 06127 then go to 06205 06205 a exchange b[p] ; A=f20eb2f10eb1fa B=f1f1f1f1f1f1f1 06206 if a >= b[p] 06207 then go to 06212 06212 a exchange b[p] ; digits match, try next nibble of instruction 06213 p - 1 -> p ; P=6 06214 if a >= b[p] 06215 then go to 06220 06220 a exchange b[p] ; A=f20eb2f10eb1fa B=f1f1f1f1f1f1f1 06221 if a >= b[p] 06222 then go to 06225 ; both nibble match - found target 06225 c + 1 -> c[xs] ; C=0000000000002f 06226 p - 1 -> p ; P=5 06227 p - 1 -> p ; P=4 06230 if p # 12 06231 then go to 06225 ; C=0000000000012f P=2 ; C=0000000000022f P=0 ; C=0000000000032f P=12 (C=pc where target found) 06230 if p # 12 06231 then go to 06225 06232 c + 1 -> c[xs] ; C=0000000000042f 06233 c + 1 -> c[xs] ; C=0000000000052f 06234 c + 1 -> c[xs] ; C=0000000000062f 06235 decimal 06236 0 - c - 1 -> c[xs] ; C=0000000000032f 06237 c -> a[w] ; A=0000000000032f 06240 m1 -> c ; C=00000000000000 06241 b exchange c[w] ; B=00000000000000 C=f1f1f1f1f1f1f1 06242 delayed rom 00 06243 jsb 0004 ; ram[61] -> C=0000000000052f 06244 if 0 = s 8 06245 then go to 06262 06246 a exchange c[w] ; A=0000000000052f C=0000000000032f 06247 p <- 11 ... *** ram[61]=0000000052f32f 06264 delayed rom 00 06265 if n/c go to 0063 (00063 - 00135 tidy up) 00136 if 1 = s 2 00137 then go to 0304 00304 0 -> s 15 00305 if 0 = s 15 00306 then go to 0353 00353 CRC 500 00354 jsb 0004 (ram[61]->C C=0000000052f32f) 00355 jsb 0011 (get instruction n from br to a[1,0]) ; *** ram_addr=47 C=f20eb2f10eb1fa => A=0eb1faf20eb2f1 (00356 - 06026) A=000000000000f1 F=00000000000000 M1=0eb1faf20eb2f1 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address 06017 delayed rom 00 ... *** ram_addr=48 +13 C=0000000052f32f *** ram[61]=0000000052f22f *** ram_addr=48 +13 C=0000000052f22f *** ram_addr=47 C=f20eb2f10eb1fa A=f10eb1faf20eb2 F=00000000000000 M1=0eb1faf20eb2f1 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000f2f D=00000000000000 S=..2......9...... P=0 (00356 - 06026) A=000000000000b2 F=00000000000000 M1=f10eb1faf20eb2 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; b2 = GSB 2 06013 if n/c go to 06052 *** ram_addr=50, 48+13 -> C, C=0000000052f22f, look for "f2" *** ram_addr=47, C=f20eb2f10eb1fa *** ram_addr=50, 48+13 ->C, C=0000000052f22f *** ram[61]=0000052f22f02f ... (00063 - 00135) 00136 if 1 = s 2 00137 then go to 0304 00304 0 -> s 15 00305 if 0 = s 15 00306 then go to 0353 00353 CRC 500 00354 jsb 0004 *** ram_addr=48, +13, C=0000052f22f02f 00355 jsb 0011 (get instruction n from br to a[1,0]) *** ram_addr=47 C=f20eb2f10eb1fa A=0eb2f10eb1faf2 F=00000000000000 M1=00000000000000 B=00000000000000 E=00000000000000 M2=00000000000000 C=0000000052ff2f D=00000000000000 S=..2......9...... P=0 (00356 - 06026) A=0000000052f0f2 F=00000000000000 M1=0eb2f10eb1faf2 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; f2 = f LBL 2 06017 delayed rom 00 *** ram_addr=48, +13, C=0000052f22f02f *** ram[61]=0000052f22f62e *** ram_addr=48 +13, C=0000052f22f62e *** ram_addr=46, C=0ef40eb4f30eb3 A=0ef40eb4f30eb3 F=00000000000000 M1=0eb2f10eb1faf2 B=00000000000000 E=00000000000000 M2=00000000000000 C=0000000052ff2e D=00000000000000 S=..2......9...... P=0 (00356 - 06026) A=0000000052f0b3 F=00000000000000 M1=0ef40eb4f30eb3 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; b3 = GSB 3 06013 if n/c go to 06052 *** ram_addr=51 48+13, C=0000052f22f62e *** ram_addr=46, C=0ef40eb4f30eb3 *** ram_addr=51, 48+13, -> c, C=0000052f22f62e *** ram[61]=0052f22f62e42e (00063 - 00135) 00136 if 1 = s 2 00137 then go to 0304 00304 0 -> s 15 00305 if 0 = s 15 00306 then go to 0353 00353 CRC 500 00354 jsb 0004 *** ram_addr=48 00007 data register -> c 13 C=0052f22f62e42e D=00000000000000 S=..2......9...... P=0 00355 jsb 0011 *** ram_addr=46 00013 data -> c C=0ef40eb4f30eb3 D=00000000000000 S=..2......9...... P=0 ... A=0eb30ef40eb4f3 F=00000000000000 M1=00000000000000 B=00000000000000 E=00000000000000 M2=00000000000000 C=0000052f22ff2e D=00000000000000 S=..2......9...... P=0 (00356 - 06026) A=0000052f22f0f3 F=00000000000000 M1=0eb30ef40eb4f3 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; f3 = f LBL 3 06017 delayed rom 00 *** ram_addr=48; 02663 data register -> c 13; C=0052f22f62e42e 00024 c -> data register 13 *** ram[61]=0052f22f62e32e *** ram_addr=48; 00007 data register -> c 13; C=0052f22f62e32e *** ram_addr=46; 00013 data -> c; C=0ef40eb4f30eb3 A=f30eb30ef40eb4 F=00000000000000 M1=0eb30ef40eb4f3 B=00000000000000 E=00000000000000 M2=00000000000000 C=0000052f22ff2e D=00000000000000 S=..2......9...... P=0 (00356 - 06026) A=0000052f22f0b4 F=00000000000000 M1=f30eb30ef40eb4 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; b4 = GSB 4 06013 if n/c go to 06052 *** ram_addr=52; 00007 data register -> c 13; C=0052f22f62e32e ; search for f4 *** ram_addr=46; 06123 data -> c; C=0ef40eb4f30eb3 *** ram_addr=52; 00007 data register -> c 13; C=0052f22f62e32e *** ram[61]=0022f62e32e12e *** ram_addr=48; 00007 data register -> c 13; C=0022f62e32e12e *** ram_addr=46; 00013 data -> c; C=0ef40eb4f30eb3 A=0052f22f62e0f4 F=00000000000000 M1=0eb4f30eb30ef4 B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; f4 = f LBL 4 06017 delayed rom 00 *** ram_addr=48; 02663 data register -> c 13; C=0022f62e32e12e 00024 c -> data register 13 *** ram[61]=0022f62e32e02e *** ram_addr=48; 00007 data register -> c 13; C=0022f62e32e02e *** ram_addr=46; 00013 data -> c; C=0ef40eb4f30eb3 (00356 - 06026) A=0052f22f62e00e F=00000000000000 M1=f40eb4f30eb30e B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; 0e = h RTN 06000 if n/c go to 06034 06034 decimal 06035 shift left a[x] ; A=0052f22f62e0e0 06036 delayed rom 015 06037 a -> rom address 06416 if n/c go to 06514 06514 delayed rom 016 06515 if n/c go to 07267 07267 b exchange c[w] ; B=00000000000000 C=00000000000000 07270 p <- 1 07271 load constant 3 ; C=00000000000030 P=0 07272 c -> addr *** ram_addr=48 07273 data register -> c 13 ; C=0022f62e32e02e 07274 if 1 = s 1 ; ?sst 07275 then go to 07300 07276 if 0 = s 2 ; ?running 07277 then go to 06363 07300 0 -> c[s] ; C=0022f62e32e02e 07301 shift right c[w] ; C=00022f62e32e02 07302 shift right c[w] ; C=000022f62e32e0 07303 shift right c[w] ; C=0000022f62e32e 07304 if c[w] # 0 07305 then go to 07310 07310 c -> data *** ram[61]=0000022f62e32e 07311 if 1 = s 1 07312 then go to 07306 07313 delayed rom 00 07314 if n/c go to 0074 00074 b -> c[w] ; C=00000000000000 00075 1 -> s 9 ; S=..2......9...... 00076 0 -> s 12 ; S=..2......9...... 00077 if n/c go to 0124 00124 CRC 1300 ; ?C merge 00125 binary 00126 0 -> s 3 ; S=..2......9...... 00127 delayed rom 02 00130 jsb 01205 ; 0 -> s 4 6 7 8 10 13 00131 CRC 1500 ; ?C pause 00132 if 1 = s 3 00133 then go to 0257 00134 jsb 0116 *** ram_addr=48; 02663 data register -> c 13; C=0000022f62e32e 00024 c -> data register 13 *** ram[61]=0000022f62e22e 00135 b -> c[w] ; C=00000000000000 00136 if 1 = s 2 00137 then go to 0304 00304 0 -> s 15 ; S=..2......9...... 00305 if 0 = s 15 00306 then go to 0353 00353 CRC 500 00354 jsb 0004 *** ram_addr=48; 00007 data register -> c 13; C=0000022f62e22e 00355 jsb 0011 *** ram_addr=46; 00013 data -> c; C=0ef40eb4f30eb3 A=b4f30eb30ef40e F=00000000000000 M1=f40eb4f30eb30e B=00000000000000 E=00000000000000 M2=00000000000000 C=0052f22f62ef2e D=00000000000000 S=..2......9...... P=0 00356 display toggle 00357 a exchange c[w] ... A=0052f22f62e00e F=00000000000000 M1=b4f30eb30ef40e B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; 0e RTN 06000 if n/c go to 06034 *** ram_addr=48; 07273 data register -> c 13; C=0000022f62e22e 07310 c -> data *** ram[61]=0000000022f62e ... 00134 jsb 0116 *** ram_addr=48; 02663 data register -> c 13; C=0000000022f62e 00024 c -> data register 13 *** ram[61]=0000000022f52e 00135 ... *** ram_addr=48; 00007 data register -> c 13; C=0000000022f52e 00355 jsb 0011 *** ram_addr=46; 00013 data -> c; C=0ef40eb4f30eb3 00356 ... A=0052f22f62e00e F=00000000000000 M1=b30ef40eb4f30e B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; 0e RTN 06000 if n/c go to 06034 *** ram_addr=48; 07273 data register -> c 13; 07310 c -> data *** ram[61]=0000000000022f 00134 jsb 0116 *** ram_addr=48; 02663 data register -> c 13; C=0000000000022f 00024 c -> data register 13 *** ram[61]=0000000000012f 00135 ... *** ram_addr=48; 00007 data register -> c 13; C=0000000000012f 00355 jsb 0011 *** ram_addr=47; 00013 data -> c; C=f20eb2f10eb1fa 00356 ... A=0052f22f62e00e F=00000000000000 M1=b2f10eb1faf20e B=00000000000000 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=..2......9...... P=12 06027 a -> rom address ; 0e RTN 06000 if n/c go to 06034 *** ram_addr=48; 07273 data register -> c 13; C=0000000000012f 07300 0 -> c[s] ; C=0000000000012f 07301 shift right c[w] ; C=00000000000012 07302 shift right c[w] ; C=00000000000001 07303 shift right c[w] ; C=00000000000000 07304 if c[w] # 0 07305 then go to 07310 ; h RTN w/o a return address 07306 delayed rom 00 07307 if n/c go to 0061 00061 0 -> s 2 ; not running 00062 jsb 0022 00022 delayed rom 05 00023 if n/c go to 02660 02660 p <- 1 02661 load constant 3 ; C=00000000000030 P=0 02662 c -> addr *** ram_addr=48 02663 data register -> c 13 ; C=0000000000012f 02664 c - 1 -> c[xs] ; C=0000000000002f 02665 if n/c go to 02704 02704 delayed rom 00 02705 if n/c go to 0024 00024 c -> data register 13 *** ram[61]=0000000000002f 00025 return 00063 1 -> s 9 ; S=.........9...... 00064 binary 00065 CRC 1500 ; ?C pause 00066 CRC 1300 ; ?C merge 00067 0 -> s 12 ; S=.........9...... 00070 delayed rom 02 00071 jsb 01205 ; 0 -> s 4 6 7 8 10 13 00072 if n/c go to 0135 00135 b -> c[w] ; C=00000000000000 00136 if 1 = s 2 00137 then go to 0304 00140 0 -> c[w] ; C=00000000000000 00141 0 -> s 1 00142 0 -> s 3 ; S=.........9...... 00143 0 -> c[s] ; C=00000000000000 00144 m1 exch c ; M1=00000000000000 C=b2f10eb1faf20e 00145 if 1 = s 11 00146 then go to 0317 00147 delayed rom 017 00150 jsb 07706 *** ram_addr=62; 07711 data register -> c 15; C=00000000000000 00151 a exchange b[w] ; A=00000000000000 B=0052f22f62e0e0 00152 a -> b[w] ; B=00000000000000 00153 if 1 = s 12 00154 then go to 0157 00155 delayed rom 04 00156 jsb 02007 *** ram_addr=48; 02013 data register -> c 14; C=00000012220000 ... A=70000000000000 F=00000000000000 M1=00000000000000 B=00000000000000 E=00000000000000 M2=00000000000000 C=72000002220100 D=00000000000000 S=.........9...... P=12 00157 delayed rom 02 00160 jsb 01162 ... A=0000fffffff100 F=00000000000000 M1=00000000000000 B=03000000000022 E=00000000000000 M2=00000000000000 C=00000000000000 D=00000000000000 S=.........9...... P=11 00161 hi im woodstock 00162 display off 00163 display toggle 00164 0 -> s 15 00165 if 1 = s 15 00166 then go to 0164 (00167 - 00213 wait loop)