This is a work in progress and likely to be updated.<\/p>\n
The HP67 Arithmetic, Control and Timing chip (ACT) is a Mostek MK6216N. It understands most of the instructions but the HP67 card reader chip (CRC, a Mostek MK6250N) adds instructions and two more data registers:<\/p>\n
Default Functions Flag. (ie if no program loaded. A-E do 1\/x etc.)
\nCRC 1000 = Set.
\nCRC 1100 = Test. If flag s[3]=1. Clear flag.<\/p>\n
Write mode (data or prog)
\nCRC 660 = Set.
\nCRC 760 = Clear.<\/p>\n
Merge Flag
\nCRC 1200 = Set.
\nCRC 1300 = Test. If flag s[3]=1. Clear flag.<\/p>\n
“a key was pressed” flag.
\nCRC 400 = Set.
\nCRC 500 = Test. If flag s[3]=1. Clear flag.<\/p>\n
“waiting for side 2” flag.
\nCRC 1400 = Set.
\nCRC 1500 = Test. If flag s[3]=1. Clear flag.<\/p>\n
???display_digits???
\nCRC 60 = Set.
\nCRC 160 = Test. If flag s[3]=1. Clear flag.<\/p>\n
CRC 300 = Test W\/PRGM switch. If … s[3]=1.<\/p>\n
CRC 560 = Test card inserted. If … s[3]=1.<\/p>\n
CRC 100 = Test ready. If ready s[3]= 1. Clear card inserted.<\/p>\n
CRC 360 = Motor off.<\/p>\n
CRC 260 = Motor on.<\/p>\n
CRC 1700 = RW (read\/write 7 nibbles fm\/to card)<\/p>\n
0x99 Write data (to go to card) – only the lhs (7 nibbles get written).
\n0x9b Read data (from card) – same 7 nibbles appear in lhs and rhs eg 12345671234567.<\/p>\n
\r\n13211 if 1 = s 3 \r\n13212 then go to 013406\r\n13213 return \r\n13154 a exchange c[w] \t; a is chksum (left 7 nibbles) and n (15..0) from ram[base+n]\r\n13155 c - 1 -> c[p] \t; n=n-1\r\n13156 if n\/c go to 013125\r\n13125 c -> addr \r\n13126 b exchange c[w] \r\n13127 data -> c \t; get ram[base+n]\r\n13130 0 -> a[w] \r\n13131 p <- 6 \r\n13132 c -> a[wp] \t; put rhs in a, lhs stays in c\r\n13133 rotate a left \t; move rhs, left 7 nibbles\r\n13134 rotate a left \r\n13135 rotate a left \r\n13136 rotate a left \r\n13137 rotate a left \r\n13140 rotate a left \r\n13141 rotate a left \r\n13142 0 -> c[wp] \r\n13143 a exchange b[w] \t; save in b for later\r\n13144 a + b -> a[w]\t; update chksum \r\n13145 a + c -> a[w] \t; update chksum\r\n13146 jsb 013162\t; select ram[0x99]\r\n13162 p <- 1 \r\n13163 load constant 9 \r\n13164 load constant 9 \r\n13165 c -> addr \r\n13166 return \r\n13147 c -> data \t; write c to ram[0x99]\r\n13150 jsb 013201\t; wait for crc to be ready\r\n13201 0 -> s 3 \r\n13202 CRC 100 \r\n13203 if 0 = s 3 \r\n13204 then go to 013202\r\n13205 binary \r\n13206 p <- 0 \r\n13207 0 -> s 3 \r\n13210 CRC 1700 \t\t; write data to card\r\n13211 if 1 = s 3 \r\n13212 then go to 013406\t; probably error writing\r\n13213 return \r\n\r\n13151 b exchange c[w] \t; write what was in b (ram[..].rhs << 7)\r\n13152 c -> data \r\n13153 jsb 013201\t; wait for crc to be ready\r\n13201 0 -> s 3 \r\n13202 CRC 100 \r\n13203 if 0 = s 3 \r\n13204 then go to 013202\r\n13205 binary \r\n13206 p <- 0 \r\n13207 0 -> s 3 \r\n13210 CRC 1700 \t\t; write\r\n13211 if 1 = s 3 \r\n13212 then go to 013406\r\n13213 return \r\n<\/pre>\nRead<\/h2>\n
\r\n12650: b exchange c[w]\r\n12651: jsb 012644 ; select ram bank 3 (addr=48)\r\n12652: b -> c[w]\r\n12653: c -> data register 15\r\n12654: a -> b[w]\r\n12655: data register -> c 12\r\n12656: a exchange c[w]\r\n12657: data register -> c 11\r\n12660: if 0 = s 8\r\n12661: then go to 012670\r\n12662: if a >= c[m]\r\n12663: then go to 012670\r\n;\r\n; update counters but don't save anything (g MERGE)\r\n12664: c - 1 -> c[m]\r\n12665: c -> data register 11\r\n12666: data register -> c 15\r\n12667: if n\/c go to 012677\r\n;\r\n; update counters and save b in ram[ram[48+15]]\r\n12670: c - 1 -> c[m]\r\n12671: c -> data register 11\r\n12672: data register -> c 15\r\n12673: c -> addr\r\n12674: b exchange c[w]\r\n12675: c -> data ; save ram[i]= lhs.rhs\r\n12676: b exchange c[w]\r\n;\r\n; finish up\r\n12677: p <- 3\r\n12700: return\r\n<\/pre>\nAsk for Card<\/h2>\n
\r\n13614: if 1 = s 13 \r\n13615: then go to 013657 \r\n13616: 0 -> b[w] \r\n13617: p <- 13 \r\n13620: load constant 11 ; 'C'\r\n13621: load constant 10 ; 'r'\r\n13622: load constant 13 ; 'd'\r\n13623: 0 -> c[wp] ; set rest to 0xffffff...\r\n13624: c -> a[w] \r\n13625: a - 1 -> a[wp] \r\n13626: display toggle ; show \"Crd \"\r\n13627: 0 -> s 3 \r\n;\r\n; clear key press\r\n13630: 0 -> s 15 \r\n13631: if 1 = s 15 \r\n13632: then go to 013630 \r\n;\r\n; wait for card inserted or key press\r\n13633: if 1 = s 15 \r\n13634: then go to 013641 ; key pressed \r\n13635: CRC 560 ; if card inserted s 3 = 1 \r\n13636: if 0 = s 3 \r\n13637: then go to 013633 \r\n13640: return ; card inserted\r\n<\/pre>\nCard Format<\/h1>\n
For<\/p>\n
46: 00000000000e37\r\n47: 12131e153919fa\r\n<\/pre>\nand W\/PRGM<\/p>\n
\r\n*** CardWrite 0: 0000000\t; sync x 3\r\n*** CardWrite 1: 0000000\r\n*** CardWrite 2: 0000000\r\n*** CardWrite 3: 3100222\t; status\r\n*** CardWrite 4: 12131e1\tram[47] lhs\r\n*** CardWrite 5: 53919fa\tram[47] rhs\r\n*** CardWrite 6: 0000000\tram[46] lhs\r\n*** CardWrite 7: 0000e37\tram[46] rhs\r\n*** CardWrite 8: 0000000\r\n*** CardWrite 9: 0000000\r\n*** CardWrite 10: 0000000\r\n*** CardWrite 11: 0000000\r\n*** CardWrite 12: 0000000\r\n*** CardWrite 13: 0000000\r\n*** CardWrite 14: 0000000\r\n*** CardWrite 15: 0000000\r\n*** CardWrite 16: 0000000\r\n*** CardWrite 17: 0000000\r\n*** CardWrite 18: 0000000\r\n*** CardWrite 19: 0000000\r\n*** CardWrite 20: 0000000\r\n*** CardWrite 21: 0000000\r\n*** CardWrite 22: 0000000\r\n*** CardWrite 23: 0000000\r\n*** CardWrite 24: 0000000\r\n*** CardWrite 25: 0000000\r\n*** CardWrite 26: 0000000\r\n*** CardWrite 27: 0000000\r\n*** CardWrite 28: 0000000\r\n*** CardWrite 29: 0000000\r\n*** CardWrite 30: 0000000\r\n*** CardWrite 31: 0000000\r\n*** CardWrite 32: 0000000\r\n*** CardWrite 33: 0000000\r\n*** CardWrite 34: 0000000\r\n*** CardWrite 35: 0000000\r\n*** CardWrite 36: 96a5c34\t; chksum x2\r\n*** CardWrite 37: 96a5c34\r\n<\/pre>\nStatus<\/h1>\n
c6 c5 c4 c3 c2 c1c0<\/p>\n
c6= 1 Data, 2 Data#2 (sec).
\n 3 Prog (001-112), 4 Prog Side 2 (steps 113-224).
\nThere are 7 steps per register, 16 registers per side, =112 steps).<\/p>\nc5= 1 if single side, 0 if either part of 2 sided card.<\/p>\n
c4= (F0?8:0)+(F1?4:0)+(F2?2:0)+(F3?1:0)<\/p>\n
c3= 0 DEG, 1 RAD, 2 GRAD<\/p>\n
c2= dsp (eg 3 for DSP 3, 2 for DSP 2)<\/p>\n
c1c0= 22 FIX, 40 ENG, 00 SCI<\/p>\n
More Detail<\/h1>\n
I have created commented \/ summarized listings for:
\nwriting a HP-67 program to a mag card<\/a>
\nreading a HP-67 program from a mag card<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"This is a work in progress and likely to be updated. The HP67 Arithmetic, Control and Timing chip (ACT) is a Mostek MK6216N. It understands most of the instructions but the HP67 card reader chip (CRC, a Mostek MK6250N) adds instructions and two more data registers:<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[16,5,3],"tags":[33,32],"_links":{"self":[{"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/posts\/1152"}],"collection":[{"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/comments?post=1152"}],"version-history":[{"count":18,"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/posts\/1152\/revisions"}],"predecessor-version":[{"id":1357,"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/posts\/1152\/revisions\/1357"}],"wp:attachment":[{"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/media?parent=1152"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/categories?post=1152"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.sydneysmith.com\/wordpress\/wp-json\/wp\/v2\/tags?post=1152"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}