This needs more analysis, but here’s what happens when you press [f] [CL PRGM]

HP67 Logging started.

; wait loop
00167 0 -> s 3
00170 CRC 1500
00171 if 1 = s 3
00172 then go to 0263
00173 0 -> s 1
00174 CRC 300
00175 if 1 = s 3
00176 then go to 0204
00204 if 0 = s 11
00205 then go to 0315
00206 0 -> s 3
00207 CRC 560
00210 if 1 = s 3
00211 then go to 01324
00212 if 0 = s 15
00213 then go to 0167

;
; [f] pressed
;
00214 display off
00215 b exchange c[w]
00216 CRC 400          ; Set the "a key was pressed" flag
00217 keys to a
00220 0 -> c[x]
00221 a exchange c[xs]
00222 shift right a[x]
00223 p <- 0
00224 load constant 5
00225 a + c -> a[x]
00226 c - 1 -> c[xs]
00227 if n/c go to 0225
(00225 - 00227)
00230 a - c -> a[x]
00231 shift left a[x]
00232 0 -> c[x]
00233 p <- 2
00234 load constant 4
00235 0 -> s 3
00236 if 0 = s 4
00237 then go to 0254
00254 m1 exch c
00255 delayed rom 03
00256 a -> rom address
I
01411 if n/c go to 01572
01572 if 1 = s 4
01573 then go to 01600
01574 if 1 = s 6
01575 then go to 01600
01576 jsb 01741

.01741 0 -> s 4
.01742 0 -> s 6
.01743 0 -> s 7
.01744 0 -> s 8
.01745 0 -> s 13
.01746 return

01577 if n/c go to 01601
01601 1 -> s 4
01602 1 -> s 6
01603 if n/c go to 01570
01570 delayed rom 01
01571 if n/c go to 0451
00451 1 -> s 13
00452 delayed rom 00
00453 if n/c go to 0142
00142 0 -> s 3
00143 0 -> c[s]
00144 m1 exch c
00145 if 1 = s 11
00146 then go to 0317
00317 jsb 0004

.00004 p <- 1
.00005 load constant 3
.00006 c -> addr
.*** ram_addr=48
.00007 data register -> c 13
.00010 return

00320 delayed rom 02
00321 if n/c go to 01117
01117 delayed rom 04
01120 jsb 02362

.02362 decimal
.02363 0 -> c[ms]
.02364 0 -> a[w]
.02365 p <- 1
.02366 if c[p] = 0
.02367 then go to 02412
.02412 p <- 10
.02413 binary
.02414 a - 1 -> a[wp]
.02415 return

01121 m1 -> c
01122 a exchange c[ms]
01123 if 1 = s 13
01124 then go to 01127
01127 m1 exch c
01130 data register -> c 13
01131 if c[x] # 0
01132 then go to 0322
01133 m1 -> c
01134 0 -> c[x]
01135 c - 1 -> c[x]
01136 a exchange c[w]
01137 a exchange c[x]
01140 b exchange c[w]
01141 0 -> b[w]
01142 if n/c go to 01115
01115 delayed rom 00
01116 if n/c go to 0327
00327 if 1 = s 11
00330 then go to 0161
I
00161 hi im woodstock
00162 display off
00163 display toggle
00164 0 -> s 15
00165 if 1 = s 15
00166 then go to 0164
(00167 - 00213 wait loop)

;
;[CL PRGM] pressed
;
(00214 - 00237 as above)
00240 if 0 = s 6
00241 then go to 0254
00242 a + c -> a[xs]
00243 if 1 = s 8
00244 then go to 0251
00245 a + c -> a[xs]
00246 if 1 = s 7
00247 then go to 0251
00250 a + c -> a[xs]
00251 m1 exch c
00252 delayed rom 01
00253 a -> rom address
I
00717 if n/c go to 0472
00472 delayed rom 02
00473 if n/c go to 01062
01062 if 0 = s 11
01063 then go to 0125
01064 0 -> c[w]
;
; set default functions flag. ie no program loaded.
;
01065 CRC 1000
;
; clear ram bank 2 (ram[32..47])
;
01066 p <- 1
01067 load constant 2
01070 jsb 01047

.01047 a exchange c[w]
.01050 binary
.01051 0 -> c[w]
.01052 a - 1 -> a[p]
.01053 a exchange c[w]
.01054 c -> addr
.*** ram_addr=47
.01055 a exchange c[w]
.01056 c -> data
.*** ram[47]=00000000000000
.01057 a - 1 -> a[p]
.01060 if n/c go to 01053
.01053 a exchange c[w]
.01054 c -> addr
.*** ram_addr=46
.01055 a exchange c[w]
.01056 c -> data
.*** ram[46]=00000000000000
.01057 a - 1 -> a[p]
.01060 if n/c go to 01053
.(etc)
.01053 a exchange c[w]
.01054 c -> addr
.*** ram_addr=32
.01055 a exchange c[w]
.01056 c -> data
.*** ram[32]=00000000000000
.01057 a - 1 -> a[p]
.01060 if n/c go to 01053
.01061 return

;
; clear ram bank 1 (ram[16..31])
;
01071 p <- 1
01072 load constant 1
01073 jsb 01047

.01047 a exchange c[w]
.(as above but)
.*** ram[31]=00000000000000
.*** ram[30]=00000000000000
.(etc)
.*** ram[16]=00000000000000
.01057 a - 1 -> a[p]
.01060 if n/c go to 01053
.01061 return

01074 jsb 01036

.01036 delayed rom 00
.01037 jsb 0004

..00004 p <- 1
..00005 load constant 3
..00006 c -> addr
..*** ram_addr=48
..00007 data register -> c 13
..00010 return

.01040 0 -> c[w]
.01041 c -> data register 13
.*** ram[61]=00000000000000
.01042 return

01075 c -> data register 14
*** ram[62]=00000000000000
01076 if n/c go to 01010
01010 data register -> c 14
01011 if c[w] # 0
01012 then go to 01023
; set default functions flag. ie no program loaded. A-E do 1/x etc.
01013 CRC 1000
01014 0 -> c[w]
01015 p <- 7
01016 load constant 1
01017 load constant 2
01020 load constant 2
01021 load constant 2
01022 c -> data register 14
*** ram[62]=00000012220000
01023 jsb 01036

.01036 delayed rom 00
.01037 jsb 0004

..00004 p <- 1
..00005 load constant 3
..00006 c -> addr
..*** ram_addr=48
..00007 data register -> c 13
..00010 return

.01040 0 -> c[w]
.01041 c -> data register 13
.*** ram[61]=00000000000000
.01042 return

01024 p <- 1
01025 c + 1 -> c[p]
01026 c -> addr
*** ram_addr=16
01027 clear data registers
01030 c + 1 -> c[p]
01031 c -> addr
*** ram_addr=32
01032 clear data registers
01033 clear s
01034 delayed rom 00
01035 if n/c go to 0074
00074 b -> c[w]
00075 1 -> s 9
00076 0 -> s 12
00077 if n/c go to 0124
00124 CRC 1300 ; test/clear merge flag
00125 binary
00126 0 -> s 3
00127 delayed rom 02
00130 jsb 01205

.01205 0 -> s 4
.01206 0 -> s 6
.01207 0 -> s 7
.01210 0 -> s 8
.01211 0 -> s 10
.01212 0 -> s 13
.01213 return

00131 CRC 1500 ; test/clear Crd flag
00132 if 1 = s 3
00133 then go to 0257
00134 jsb 0116

.00116 if 1 = s 2
.00117 then go to 0122
.00120 if 0 = s 1
.00121 then go to 0123
.00123 return

00135 b -> c[w]
00136 if 1 = s 2
00137 then go to 0304
00140 0 -> c[w]
00141 0 -> s 1
00142 0 -> s 3
00143 0 -> c[s]
00144 m1 exch c
00145 if 1 = s 11
00146 then go to 0317
00147 delayed rom 017
00150 jsb 07706

.07706 p <- 1 
.07707 load constant 3 
.07710 c -> addr 
.*** ram_addr=48
.07711 data register -> c 15
.07712 return 

00151 a exchange b[w]
00152 a -> b[w]
00153 if 1 = s 12
00154 then go to 0157
00155 delayed rom 04
00156 jsb 02007

.02007 p <- 1
.02010 load constant 3
.02011 c -> addr
.*** ram_addr=48
.02012 0 -> s 3
.02013 data register -> c 14
.02014 decimal
.02015 jsb 02137

..02137 c -> a[w]
..02140 0 -> c[w]
..02141 p <- 3
..02142 0 -> a[wp]
..02143 p <- 6
..02144 a exchange c[wp]
..02145 c -> a[p]
..02146 c - 1 -> c[s]
..02147 a - 1 -> a[p]
..02150 if n/c go to 02146
..(02146 - 02150) x 2
..02151 c -> a[s]
..02152 p <- 12
..02153 c - 1 -> c[p]
..02154 a - 1 -> a[s]
..02155 if n/c go to 02153
..(02153 - 02155) x 7
..02156 return

.02016 if 1 = s 3
.02017 then go to 02023
.02020 p <- 4
.02021 if c[p] # 0
.02022 then go to 02066
.02066 p <- 6
.02067 b -> c[x]
.02070 if c[xs] = 0
.02071 then go to 02124
.02124 if c[x] = 0
.02125 then go to 02116
.02116 if 1 = s 3
.02117 then go to 02105
.02120 jsb 02162

..02162 p <- 3
..02163 c -> a[w]
..02164 c + 1 -> c[s]
..02165 a - 1 -> a[p]
..02166 if n/c go to 02164
..02167 c - 1 -> c[s]
..02170 0 -> s 3
..02171 p <- 12
..02172 a exchange b[wp]
..02173 a -> b[wp]
..02174 if b[m] = 0
..02175 then go to 02232
..02232 return

.02121 if 0 = s 3
.02122 then go to 02105
.02105 c + 1 -> c[xs]
.02106 if n/c go to 02063
.02063 binary
.02064 0 -> s 3
.02065 return

00157 delayed rom 02
00160 jsb 01162

.01162 jsb 01143

..01143 c -> a[x]
..01144 if b[s] = 0
..01145 then go to 01147
..01147 p <- 12
..01150 shift right c[wp]
..01151 if c[xs] = 0
..01152 then go to 01156
..01156 shift right c[wp]
..01157 shift right c[wp]
..01160 shift right c[wp]
..01161 return

.01163 p <- 3
.01164 shift left a[w]
.01165 0 -> c[m]
.I
.01166 if c[s] = 0
.01167 then go to 01174
.01170 p + 1 -> p
.01171 a - 1 -> a[p]
.01172 c - 1 -> c[s]
.01173 if n/c go to 01166
.(01166 - 01173) x 6
.01166 if c[s] = 0
.01167 then go to 01174
.I
.01174 if c[xs] = 0
.01175 then go to 01201
.01176 c - 1 -> c[xs]
.01177 p + 1 -> p
.01200 if n/c go to 01174
.(01174 - 01200)
.01174 if c[xs] = 0
.01175 then go to 01201
.I
.01201 shift right a[wp]
.01202 load constant 3
.01203 b exchange c[w]
.01204 return

00161 hi im woodstock
00162 display off
00163 display toggle
00164 0 -> s 15
00165 if 1 = s 15
00166 then go to 0164
00167 0 -> s 3
00170 CRC 1500
00171 if 1 = s 3
00172 then go to 0263
00173 0 -> s 1
00174 CRC 300
00175 if 1 = s 3
00176 then go to 0204
00204 if 0 = s 11
00205 then go to 0315
I
00315 b exchange c[w]
00316 1 -> s 11
00317 jsb 0004

.00004 p <- 1
.00005 load constant 3
.00006 c -> addr
.*** ram_addr=50
.00007 data register -> c 13
.00010 return

00320 delayed rom 02
00321 if n/c go to 01117
01117 delayed rom 04
01120 jsb 02362

.02362 decimal
.02363 0 -> c[ms]
.02364 0 -> a[w]
.02365 p <- 1
.02366 if c[p] = 0
.02367 then go to 02412
.02412 p <- 10
.02413 binary
.02414 a - 1 -> a[wp]
.02415 return

01121 m1 -> c
01122 a exchange c[ms]
01123 if 1 = s 13
01124 then go to 01127
01125 0 -> c[x]
01126 jsb 01205

.01205 0 -> s 4
.01206 0 -> s 6
.01207 0 -> s 7
.01210 0 -> s 8
.01211 0 -> s 10
.01212 0 -> s 13
.01213 return

01127 m1 exch c
01130 data register -> c 13
01131 if c[x] # 0
01132 then go to 0322
01133 m1 -> c
01134 0 -> c[x]
01135 c - 1 -> c[x]
01136 a exchange c[w]
01137 a exchange c[x]
01140 b exchange c[w]
01141 0 -> b[w]
01142 if n/c go to 01115
01115 delayed rom 00
01116 if n/c go to 0327
00327 if 1 = s 11
00330 then go to 0161
I
00161 hi im woodstock
00162 display off
00163 display toggle
00164 0 -> s 15
00165 if 1 = s 15
00166 then go to 0164

(00167 - 00213 wait loop) x 2

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